Department: Electrical & Computer Engineering
Faculty Advisor(s):
Sadik Esener
Primary Student
Name: Hod Finkelstein
Email: hfinkels @ ucsd.edu
Phone: 858-822-1295
Grad Year: 2007
Abstract
Silicon single-photon avalanche diodes have been used in diverse applications, from LIDAR to single molecule imaging. When operated in Geiger-mode, these devices must withstand electric fields in excess of 1 MV/cm (the breakdown field of silicon), instantaneous current densities above 0.3 uA/um2, and operate at voltages far higher than those of standard CMOS devices. As a result, SPADs have traditionally been manufactured using custom processes, with the required timing and processing circuitry being bonded off-chip. More recently, a CMOS SPAD has been manufactured on a 0.8 um high-voltage commercial process but with poor fill factor. The manufacture of SPADs in commercial processes is highly desirable because of the low defect densities of these processes, the ability to reduce the diodes? capacitance by on-chip integration of the timing circuitry, and by economies of scale.
We demonstrate a new single-photon avalanche diode device, which utilizes the silicon-dioxide shallow-trench isolation (STI) structure common to all deep-submicron technologies, simultaneously as a junction planarization mechanism and as a guard-ring. This makes it possible to achieve an order-of-magnitude improvement in fill factor and in pixel area, and results in improved SPAD performance. We present numerical simulations and experimental results from a test chip incorporating passively and actively quenched devices, which was manufactured in an IBM 0.18 um technology. Due to the efficient structures, sub-10ns dead times are achievable without requiring active-quenching, creating the opportunity to integrate large arrays of these ultra-fast SPADs for use in biological imaging systems.
Related Links:
- http://www.jacobsschool.ucsd.edu/
Related Files:
- re08.gif
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