53. COMMUNICATION LATENCY AWARE LOW POWER NOC SYNTHESIS THROUGH TOPOLOGY GENERATION AND WIRE STYLE OPTIMIZATION Department: Computer Science & Engineering Faculty Advisor(s): Chung-Kuan Cheng Primary Student Name: Yuanfang Hu Email: yhu @ ucsd.edu Phone: 858-534-8174 Grad Year: 2006 Abstract Communication latency and power consumption are two competing objectives in Network-on-Chip (NoC) design. This paper proposes a novel method which unifies these two objectives in a multi-commodity flow (MCF) formulation. With an improved fully polynomial approximation algorithm, power optimal design of an $8\times 8$ NoC can be found for given average latency constraints with certain communication bandwidth requirement. Our methodology features three key characters. First, We introduce a variety of wire styles into NoC design, and incorporate latency constraints and power minimization objectives into a unified multicommodity flow (MCF) model, with simultaneous optimization on network topologies, physical embedding, and interconnect wire styles. Second, we heuristically explore a large design space of network topologies. Third, We implement and optimize the MCF solver using approximation algorithms, which is significantly faster than the commercial linear programming solver CPLEX. Experimental results suggest that (1) comparing with mesh, torus and hypercube topologies, our optimized design can improve power latency product by up to 52.1\%, 29.4\% and 35.6\%, respectively. (2) by sacrificing 2\% latency, power consumption of optimized design can be improved by up to 19.4\%, which indicates the importance of power latency co-optimization in NoC design. Related Links: Related Files: << Back to Posters or Search Results