Department: Electrical & Computer Engineering
Name: Chong Zhao
Email: chong @ ece.ucsd.edu
Grad Year: 2007
Yi Zhao, yizhao @ ece.ucsd.edu
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). Robustness insertion has been adopted to provide additional resiliency to the transient errors. However, the related design overhead might be excessive and the insertion might be inefficient. In this paper, we present an intelligent constraint-aware robustness insertion methodology to judiciously protect sequential elements in static CMOS digital circuits. Based on a configurable hardening sequential cell design and an effective robustness calibration technique, an optimization algorithm is developed to search for the optimal protection scheme under given design constraints and budgets. An integrated framework has been constructed to automate the process. Experiment results demonstrate that the proposed methodology is able to efficiently improve the transient error tolerance of VLSI circuits while keeping the protection cost within limit."
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