38. POWER DISTRIBUTION DESIGN FOR 3D INTEGRATION

Department: Computer Science & Engineering
Faculty Advisor(s): Chung-Kuan Cheng

Primary Student
Name: Amirali Shayan Arani
Email: ashayana@ucsd.edu
Phone: 858-822-5313
Grad Year: 2010

Student Collaborators
Xiang Hu, h2hu@ucsd.edu

Abstract
In this work, a framework for reliability aware through silicon via (TSV) planning is proposed for the 3D stacked silicon ICs. The worse case power noise of the 3D power delivery with local TSV failures results from the fabrication or operation is identified in both frequency and time domain. From the experimental results, we observe that single TSV failure would increase the maximum voltage variation up to 70% which could not be ignored in the nanoscale technology. The parameters of the 3D power delivery are designed such that the power distribution is reliable under local TSV failures. The 3D power distribution network is modelled and extracted in frequency domain that includes the skin effect and on-chip inductance. The spatial distribution of the power noise and reliability is analyzed to enhance the reliability of the stacked silicon under local TSV failures.

The work proposes an efficient flow for the analysis and co-design of large 3D power distribution networks (3D PDN). In this flow, the network is modeled in frequency domain and thus can take advantage of parallel computing. The proposed flow significantly reduces the CPU time while obtaining accurate results as compared to commercial simulation tools while features facilitate the reliable design.

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