60. TRADING IN THE FAST LANE USING GUSTO: AUTOMATIC GENERATION AND OPTIMIZATION OF FPGA BASED HARDWARE ACCELERATORS FOR FINANCIAL COMPUTATIONS

Department: Computer Science & Engineering
Faculty Advisor(s): Ryan Kastner

Primary Student
Name: Ali U Irturk
Email: airturk@ucsd.edu
Phone: 858-822-5313
Grad Year: 2009

Abstract
The ever increasing volume of financial data and demand for faster results has led financial organizations to seek high performance computing solutions. The addition of FPGAs (Field-Programmable Gate Arrays), as specially designed hardware units, to existing high performance computers can boost financial application performance through their ability to execute complex tasks in parallel. However, designing an FPGA based hardware accelerator is a time-consuming process; software developers and FPGA designers are looking for a faster path to FPGA hardware. Therefore, we designed a tool, GUSTO (General architecture design Utility and Synthesis Tool for Optimization) that automatically generates and optimizes FPGA based hardware accelerators for financial computations. GUSTO is the first tool of its kind to provide a mixed software/hardware system in just minutes instead of weeks. In this work, we show the effectiveness of our approach in developing an FPGA acceleration of Markowitz’ mean variance framework - the most popular approximation approach for optimal asset allocation. To the best of our knowledge, we are the first to propose hardware acceleration of the mean variance framework for optimal asset allocation using FPGAs. We implement common computation-intensive parts on a specially designed FPGA using GUSTO and show that an FPGA based accelerator produced by GUSTO provides 221× increase on performance over a software implementation.

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