199. SURFACE PINNING STUDY OF IN2O ON INGAAS SURFACE
Department: NanoEngineering
Research Institute Affiliation: Graduate Program in Materials Science and Engineering
Faculty Advisor(s):
Andrew C. Kummel
Primary Student
Name: Wilhelm I Melitz
Email: wmelitz@ucsd.edu
Phone: 858-534-3498
Grad Year: 2012
Student Collaborators
Jian Shen, jimshen@ucsd.edu
Abstract
Silicon based metal oxide semiconductor field effect transistor (MOSFET) technology is rapidly approaching theoretical physical limits. Alternative developments are needed to continue on the performance and size requirements set by the International Technology Roadmap for Semiconductors. Two current parameters being explored to continue MOSFETs development are decreasing effective oxide thickness (EOT) and increasing channel mobility. High mobility III-V compound semiconductors are a potential additional technology platform to silicon. High-k dielectric oxides are being used to achieve the lower EOT while still maintaining lower gate leakage. The key to fabricating a practical III-V or high-k dielectric MOSFET is forming an unpinned oxide-semiconductor interface with low fixed charge. In0.53Ga0.47As was chosen for its high carrier mobility, low density of thermal carriers, and ability to be grown lattice matched on semi-insulator InP substrates. Specifically, the In0.53Ga0.47As(001)-(4×2) surface was investigated for gate oxide deposition because the As rich surface shows problems, while the (4×2) surface is undetermined. We have used atomically resolved scanning tunneling microscopy (STM) images and scanning tunneling spectra (STS) to determine the atomic and electronic structure of clean InGaAs surfaces. When an In0.53Ga0.47As(001)/InP sample was annealed between 330°C and 400°C, an As-rich (2×4) reconstruction was observed by α2(2×4) and β2(2×4), containing single or double As dimers on the rows. At higher annealing temperatures between 440°C and 470°C an In/Ga-rich (4×2) surface reconstruction was observed. For temperatures between 400°C and 440°C a mixed (2×4)/(4×2)surface reconstruction is observed. Both STM and STS experiments are repeated on the gate-oxide/InGaAs semiconductor interface, with oxides such as In2O. Once oxide is deposited on the InGaAs(001)-(4×2) surface, STS measurements are performed to determine as whether the surface Fermi level is pinned or unpinned. In addition to the STS data, the results will be further supported by using scanning Kelvin probe microscopy (SKPM). In comparison, STS has poor energy resolution of roughly 100-200mV, whereas SKPM has roughly 10-50mV resolution. The energy resolution of 100mV makes studying electronic properties of InGaAs difficult because of its small bang gap of 0.74eV. With the higher resolution SKPM we can more confidently determine if the oxide shifts or pins the surface Fermi level. By combining STM, STS and SKPM a more accurate understanding of the interface between III-V semiconductor and the high-k dielectric oxide can be achieved.
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